As a transistor to be formed in a logic portion of a next generation microcomputer capable of miniaturization, a transistor including a metal gate electrode and a high dielectric constant film (high-k film) is known. As a method for forming such a transistor, so-called a gate-last process is known, the gate-last process forming a dummy gate electrode on a substrate, and then, replacing the dummy gate electrode with a metal gate electrode.
In addition, as an electrically writable/erasable nonvolatile semiconductor memory device, a memory cell including a conductive floating gate electrode or a trapping insulating film surrounded by an oxide film below the gate electrode of the MISFET is widely used. As a nonvolatile semiconductor memory device using the trapping insulating film, a MONOS (Metal Oxide Nitride Oxide Semiconductor) type split gate type cell is cited.
In the gate last process, after a silicide layer is formed on the source/drain region of various MISFETs, an element is covered with an interlayer insulating film, and then, an upper surface of the interlayer insulating film is polished to expose an upper surface of the gate electrode. For this reason, when a silicide layer is formed on a gate electrode configuring a memory cell and being made of a semiconductor film, it is required to perform a process of forming the silicide layer again after the polishing process.
Patent Document 1 (Japanese Patent Application Laid-open Publication No. 2014-154790) describes a case of mixedly mounting the memory cell and the MISFET of the logic portion, in which a silicide layer is formed on a source/drain region of the MISFET, subsequently a metal gate electrode of the MISFET is formed by the gate-last process, and then, a silicide layer is formed on the gate electrode of the memory cell.